This invention pertains to three dimensional integrated circuits and methods, of fabricating three-dimensional integrated circuits; more specifically this invention relates to methods of post-contact back end of line through-hole via integration for interconnect metallization for three-dimensional integrated circuits.
A three-dimensional integrated circuit includes two or more semiconductor chips with integrated circuits or includes two or more semiconductor wafers with integrated circuits. The semiconductor chips or semiconductor wafers are stacked together, bonded, and electrically interconnected in three dimensions, i.e., integrated within the semiconductor chips or semiconductor wafers and integrated between the semiconductor chips or semiconductor wafers. The interconnections between the chips or between the wafers are accomplished by way of through holes from the back side to the front side of one or more of the chips or one or more of the semiconductor wafers. In other words, the electrical connections between the stack of chips or stack of wafers are made by way of the through holes. Three-dimensional integrated circuits may have a large number of through holes for interconnect metallization between the semiconductor chips or between the semiconductor wafers.
Three-dimensional integrated circuits, according to some designs, will use through-hole vias that are large, high aspect ratio features with dimensions an order of magnitude or more larger than the minimum geometry features for standard technology dual damascene metallization interconnects. The through hole vias may require diameters of about 5-10 micrometers. The length for some of the through holes may be about 25 micrometers or more. Consequently, the aspect ratios for processing the through holes are extremely high in comparison to standard technologies for fabricating two-dimensional integrated circuits. Typical processes for fabricating two-dimensional integrated circuits cannot easily handle the large holes and extremely high aspect ratios that will be required for fabricating three-dimensional integrated circuits.
Furthermore, the process steps and process conditions required for forming the through hole vias to achieve three-dimensional integration are incompatible with many of the standard technology front end of line (FEOL) processes and standard back end of line (BEOL) processes used for the within wafer two-dimensional integration for fabricating semiconductor devices. Modifications to the standard FEOL processes and/or standard BEOL processes can be made but at what may be unacceptably high costs and risks. In other words, it is generally undesirable to manufacturers of semiconductor devices to develop and implement new processes. For some semiconductor fabrication processes, even minor modifications to the process can incur a substantial learning curve, which can be both time consuming and costly because of development costs and the tremendous costs associated with testing, process integration, and yield optimization.
Clearly, there is a need for device structures and processes for manufacturing substrates for three-dimensional integrated circuits that do not require extensive modifications to the standard technologies of FEOL processing or BEOL processing. The practical fabrication of three-dimensional integrated circuits will require new processes that can meet the requirements for metallization of three-dimensional integrated circuits. More specifically, there is a need for new processes capable of meeting the unusual aspect ratio requirements for through hole via metallization for three-dimensional integrated circuits while requiring little or no significant modifications to standard technology FEOL processes and BEOL processes used for the within wafer two-dimensional integration.